Our multinational client, a leading worldwide supplier of high performance optical sensors is in search of an:

Tasks and responsibilities

• Responsible for design verification of mixed signal integrated circuits, using both directed tests and constrained random regressions
• Proficiency in System Verilog and UVM including: writing checkers and assertions, customizing constraints, troubleshooting, getting functional coverage collection using cover groups etc.
• Technical and team leadership – both within the internal project DV team (digital and mixed-signal verification), but also directly supporting customers during project reviews or status calls
• Primary focus is on (digital) design verification, but proficiency with mixed signal design verification and creation / validation of models are a plus
• Creation of test benches and automated verification simulations
• Performing block level and top level design verification
• Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
• Experience with formal DV is a plus.

Qualifications

• Master’s degree in Electrical / Computer Engineering with 10 years (senior) or 5 years (staff) of experience in Design Verification
• Experience (senior) or exposure (staff) to project or technology leadership role
• System Verilog / UVM based DV experience. Formal DV experience is a plus.
• Collaborative and respectful team player with mentoring skills, and passionate about achieving team goals
• Excellent communication skills (both oral and written) are required, as real time customer level technical interface and design / team leadership is necessary.
• Experience with relevant CAD tools.
• Fluent business English