Our DACH client, a leading worldwide supplier of high performance optical sensors is in search of an:

Tasks and responsibilities

• Implementation of digital design blocks in RTL level based on requirement specification
• Perform silicon evaluation and support production test team
• Digital design based on system and block level documentations
• Maintain micro-architecture design and create design documents of design and evaluation
• Create Verification Environments for the Design to test the chip for functionality, efficiency and consistency utilizing models, checkers, monitors, assertions and transactors
• Perform design, verification of digital modules
• Work closely with Technical Lead (Digital) for chip design / system optimization to ensure low power, timing, robust design and state of the art implementation
• Develop test cases and test scripts to meet functional code coverage goals
• Create constrains for layout generation
• Create documentation
• Work with design team to resolve design and layout constraints
• Ensure that designed chip module meets customer specifications and needs
• Implement chip design guidelines to ensure reliability and re-usage
• Develop best practices to reduce power, die size and timing
• Keep commitments for schedule and quality
• Digital Simulations for the Top level (Analog IPs are replaced by Behavioral Models)
• Knowledge of bug tracking tools

Qualifications

• Degree or Diploma in Engineering
• Have 5+ years, preferable, experience in digital / mixed-signal ICs design.
• Strong knowledge of hardware description languages (VHDL, System Verilog, Verilog)
• Proven ability to optimize and develop design architecture from chip inception through to compliant netlist
• Competence in developing design constraints and Synthesis scripts (Synopsys DC)
• Proficiency in developing block and top level Timing constraints for STA and P&R handoff
• Experience in UVM methodology would be definitely a plus
• Good knowledge of digital design tools (synthesis, LEC (logic equivalence check), CDC (clock domain crossing)
• Good knowledge of concepts for testability (Scan+ATPG tests, BIST)
• Good knowledge about digital circuit simulation and verification
• Knowledge of concepts for design reuse