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Digital Design Engineer (d/m/f)

Job Title
Digital Design Engineer (d/m/f)
Job ID
27710081
Location
Rapperswil, Switzerland, St. Gallen (St. Gall), CH  CH flag 
Other Location
Description

Our Swiss client, a leading worldwide supplier of high performance sensor solutions is in search of a:

Digital Design Engineer - Rapperswil, Switzerland

 

Your tasks and responsibilities

  • Digital frontend to backend implementation: concept definition, specification, requirement mapping, architectural design, RTL in Verilog / System Verilog, synthesis including test insertion, timing analysis, place route, I/R-drop analysis, silicon sign-off, ATPG
  • Experience is preferred for: Clock gating / clock tree design, multiple power domains (UPF), mixed signal interface, I2C, SPI, microcontroller and memory embedding
  • Collaboration with customers on shared designs and with technical project lead, digital verification engineer and layout lead
  • Technical communication with internal or external customers, presentation of work status, participation in design reviews
  • Collaboration with internal departments and exchange with expert groups
  • Participation in communities of practice with the goal to support the improvement of work methodologies
  • Generation of relevant documentation

 

Your education and experiences

  • Bachelor’s degree in Electrical Engineering with focus on digital systems or at least 3 years of experience in digital design
  • High level of proficiency in digital design related design flow and related CAD tools
  • Experience in sensor applications with multiple power domains, multi-channel design and multiple clock domains a plus
  • Experience in digital verification a plus
  • Excellent team player – dedicated to achieving team goals
  • Excellent communication skills and proficiency in English and German
Required Skills

Electrical Engineering bachelors degree
Digital Design experience
English fluency
German fluency
EU citizen or Swiss permit holder
Optional Skills

Sensor applications
Digital verification
Openings
1

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