Our German client, a leading worldwide supplier of high performance semiconductor sensor solutions is in search of an:

Senior Engineer, IC Design Verification

Tasks and responsibilities

• Responsible for planning and executing digital and mixed signal verification on high performance analog / mixed-signal architectures & circuits
• Support and development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications
• Support, write, debug and run test-benches using Verilog-A/Verilog-AMS/System Verilog to verify behavioral and transistor level designs 
• Plan, architect and develop SystemVerilog/UVM/direct test benches, including writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc
• This role requires the candidate to work proactively with RTL Design, Verification, Analog, Architecture teams to ensure that chip meets all the feature requirements. Should be able to make decision on right verification methodology based on type of design
• Familiarity with systems using deeply embedded microcontrollers
• Create, debug, and run test-benches and scripts to execute transistor-level performance verification over design corners using circuit simulators
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
• Develop behavioral block level models (SystemVerilog-RNM, wreal, EEnet)
• Technical leadership in the development and execution of verification test plans and activities which includes environment setup, regressions, failure debug and netlist simulation for tape-out, develop detailed test and coverage plans based on IC and product specifications
• Prepare documents required for design reviews, internal discussions, test requirements and design documentations including DV Plan, DV execution plan, …
• Performing block level and top level design verification
• Creative problem solver, able to generate new IP and file patents
• Help junior / younger engineers learn required knowledge and experience through projects work

Your education and experiences

• Master’s or Diplom degree in Electrical Engineering or microelectronics with initial experience – with an emphasis in analog /digital / mixed signal Integrated Circuit Design or a similar specialty
• Minimum 10 years of experience in the field of IC digital / mixed design verification
• Background in digital or analog IC circuit development, design for test and semiconductor technologies
• Expertise with Cadence AMS Designer and modelling in System Verilog and developing behavioral models of mixed signal Systems
• Experience in building of test bench from scratch using UVM or System Verilog
• Strong knowledge of serial protocol like I2C, I3C, SPI etc. and its verification
• Experience with the Cadence Analog Design Environment (ADE-L/ADEXL/ Maestro) is plus
• Solid programming background (Python, Perl, etc.) familiarity with EDA tools (Virtuoso, NCVerilog, Spectre, vManager, etc.)
• Experience with Universal Verification Method (UVM) is advantageous
• Experience in verifying mixed signal blocks in digital perspective is strong benefit
• Excellent team player
• Calm professional demeanor and excellent listening skills, ability to organize and prioritize work
• Good communication skills in oral and written English and German